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This Course uses the "Course & Go" concept. This concept combines
Consultancy, Design and Education. For you it means that you just
get what you need to know for your Digital System Design. You will
not loose time listening to topics, which are far away from your
practical application. The relevant knowledge is transferred in an
interactive and intensive way. Finally Basic aim of this Course is
to make a professional capable enough to make his/her own FPGA based
systems. This course covers design simulation, verification/testing
and synthesis/implementation of FPGA based digital systems using the
standard Verilog Hardware Description Language and Synthesis Tool.
This course is heavily
Laboratory
oriented in which the participants will be designed and evaluated
digital circuits.
Computer Aided
Design (CAD) tools will be used for the experiments.
Course Outlines:
Ø What
the difference between Sequential and Concurrent Processing
Ø
Digital Chip Design using Verilog HDL with ModelSim Simulator
Ø
Controller based Designs – State Machines
Ø
Testing and Verification Methodology – Automated Test Benches
Ø
Introduction to VHDL and comparison with Verilog HDL
Ø
Xilinx FPGA Design Methodology, architecture (Spartan-II &
Spartan-III devices)
Ø
Design synthesis and implementation using Xilinx ISE 9.1i
Ø
Timing Analyzer, Core Generator, Constraint Editor, Floor Planner,
XPower and iMPACT tools
Ø
Assign pin locations with the PACE tool
Ø
Read reports to determine whether design goals were met
Ø
Strategy for Explore Critical Path of Design back to RTL
Ø
Analyze design statistics, connectivity, timing and placement result
by using PlanAhead
Ø
Real time “on-chip” debugging for Xilinx FPGA by using ChipScope Pro
(VIO,ILA & ICON) Cores
Ø
Real time simulations with Xilinx FPGA based Training Boards
Ø
Hardware Testing of FPGA based Design on Xilinx training boards
Ø
Study to build a Data Acquisitioning System with FPGA
-
Describe the structure and resources of
the various Xilinx FPGA products
-
Introduction of the Concept of
Embedded Controllers and System on Chip
Attention:
Already 503
Engineers/Scientists, mostly from Defense Organizations, have
successfully completed this course under Skill Development Council (SDC),
Govt. of Pakistan.
Prerequisites:
à
B.E Electronics / Electrical, Computer / IT Engineering, M.Sc
Electronics / Computer Science (Students are warmly welcome…)
à
Basic Fundamental of Digital Design
& Computer Architecture
à
Programming Basics (prefer C language)
* Opportunity
for Fresh Engineers to improve their skills in High Tech field of
Electronics
v
Skill Gained
after completing this course
After completing this comprehensive training, participant will have
the necessary skills to:
ü
Locate the design issues and solve them
ü
Implement digital designs using Verilog HDL
ü
Create test and verification strategy for chip designing
ü
Design an optimize state machine based designs
ü
Xilinx FPGA architecture details
ü
Synthesis, Implementation & configuration processes using ISE 9.2i
ü
Create design constraints and analyze synthesis & timing reports
ü
Use built-in resources of Xilinx FPGA in your design
ü
How to use Xilinx FPGA on PCB (FPGA configuration on Board)
ü
Use Xilinx Chip Scope Pro tools for real-time debugging
ü
Use Xilinx Plan Ahead tools for Advance Implementation Process
ü
Create Real-time testing environment with FPGA boards
v
Course Schedule
This lab-course introduces the Verilog HDL language with emphasis on
targeting Xilinx devices specifically general. This lab work also
combines insightful lecture with practical lab exercises to
reinforce key then apply this information to any digital design
using a Top-Down synthesis design approach along with proper test
and verification methodologies.
For FPGA Implementation tackles the most sophisticated aspects of
the ISE™ Suite, ModelSim SE and Xilinx hardware. Twenty labs provide
hands-on experience in this course. In addition, by mastering the
tools and the design methodologies presented in this course, you
will be able to create your design faster, shorten your development
time, and lower development costs.
|
|
Duration |
Detail |
|
Duration |
Six Weeks |
Three days per week |
|
Lectures |
Sixteen (16) |
Two hrs per lecture |
|
LABs |
Twenty (20) |
Two hrs per lab |
1st
Week:
|
DAY |
TIME |
TOPIC |
TIME |
LAB WORK |
|
1 |
2 hrs |
1.
Course Introduction.
2.
Design Methodology, Digital Design
Objective, Combinational &
Sequential Design Basics, Clock
Methodology, Critical & Cycle Time |
2 hrs |
à ModelSim
Tool Training |
|
2 |
2 hrs |
1.
Verilog HDL Basics, Verilog Value
Set,
Numbers in Verilog, Net, Register
&
Vectors, Arrays, Memories,
Parameters, Strings, System tasks,
Compiler Directives In Verilog
2.
Abstraction Levels (Switch, Gate,
Dataflow & Behavioral), Modules
&
Ports, Module instances,
Hierarchal Design Concept, Gate
Level Modeling using Examples
|
2 hrs |
à Simulation
of 1-bit ADDER/SUB
using Gate Level & Data Flow
Level in ModelSim
à Simulation
of 1-bit
MUX/DEMUX using Gate Level
& Data Flow Level in ModelSim
à Simulation
of 4-bit UX/DEMUX
using 1-bit in ModelSim
|
|
3 |
2 hrs |
1.
Continuous Assignment, Port
Assignments, Operators (Logical,
Bitwise, Reduction, Shift,
Concatenation, Relational,
Equality, Conditional, Arithmetic)
2.
Behavioral Modeling, Procedural
Blocks (initial, always) |
2 hrs |
à Simulation
of 4-bit ADDER/SUB
using bit in ModelSim
à Simulation
of implementation of
Timing Diagrams, D-FF/Register
and 4-bit Ripple Carry Counter
in
ModelSim
|
2nd
Week:
|
DAY |
TIME |
TOPIC |
TIME |
LAB WORK |
|
1 |
2 hrs |
1.
Blocking & Non-Blocking
Assignments, Clock & Async
/
Sync Reset in Digital System
Events, Combinatorial
Statements, Timing Analysis,
Delays
2.
Procedural Statements (if,
case/casex/casez, for, while, repeat,
forever), Mixed abstraction modeling
|
2 hrs |
à Design a
Single/Dual Clock RAM
and simulate in ModelSim
à Design a
FIFO and simulate in
ModelSim |
|
2 |
2 hrs |
1.
Test Bench Concept, Formation of
Test Bench, File Handling, Tasks,
Functions, Test Drivers / Vectors,
Built- in Self-Test, Boundary
Scan Testing
2.
System Tasks, Compiler Directives,
Parameters/Define Statements
|
2 hrs |
à Generate
random data & use File
Handling using Tasks to
improve
testability by using ModelSim |
|
3 |
2 hrs |
1.
Digital Systems, State Machine
Concept, Moore & Mealy State
Machines based Design, One Hot
State Machine
2. State
machine based Traffic
Controller
|
2 hrs |
à Traffic
Controller |
3rd
Week:
|
DAY |
TIME |
TOPIC |
TIME |
LAB WORK |
|
1 |
2 hrs |
1.
Behavioral/RTL Coding Techniques
(Synchronous / Asynchronous Design,
Race
Condition, Delay Dependent
Logic, Glitches, Hold Time
Violations, Gated Clocking),
Simulation / Synthesis Issues |
2 hrs |
à Design an
ADC Interface with
FPGA and Simulate in ModelSim
|
|
2 |
2 hrs |
1.
Comparison of HDL:
Verilog HDL Vs VHDL
2. RTL
Coding Guidelines |
2 hrs |
à Design a
DAC Interface with
FPGA and Simulate in ModelSim
|
|
3 |
2 hrs |
1.
Introduction of FPGA & CPLD, FPGA
& CPLD basics, Xilinx FPGA series,
FPGA Technology, FPGA
advantages, FPGA variations, FPGA
Configurable Logic Blocks (CLBs),
LUT Implementation in CLBs,
FPGA IO Blocks
2.
Xilinx XC4000 & Spartan Series
FPGA internal architecture |
2 hrs |
à Design a
DSP Processor
(Ti TMSC64x) Interface with
FPGA and Simulate in ModelSim |
4th Week:
|
DAY |
TIME |
TOPIC |
TIME |
LAB WORK |
|
1 |
2 hrs |
1.
Xilinx FPGA Design Process,
Synthesis Flow (Xilinx Synthesis
Technology),
2. Core Generator
|
2 hrs |
à Xilinx ISE
Tool Training
(Overview with Synthesis,
Implementation and
Configuration)
à Generate a
Block RAM for FIFO
by using ISE 8.1i Core
Generator
|
|
2 |
2 hrs |
1.
Timing Simulation
2.
Implementation Flow
(Translate, MAP and Place &
Route), Constraint Editor,
Functional / Timing Verification,
Floor Planner, FPGA Editor,
Configuration Flow (configuration
modes), EPROM File Formatter,
iMPACT tool basics |
2 hrs |
à Timing
Simulation of Dual Clock
RAM (with Block & Distributed)
à Use
Constraints Editor , mcs, bit
file generation |
|
3 |
2 hrs |
1.
Concepts of Digital Signal Processing
(DSP) in Field Programmable Gate
Array (FPGA) |
2 hrs |
à Design a
4-Tap FIR Filter
and Simulate in ModelSim
à Use
pipelining for increasing
design frequency |
5th Week:
|
DAY |
TIME |
TOPIC |
TIME |
LAB WORK |
|
1 |
2 hrs |
1.
Concepts of Digital Signal Processing
(DSP) in Field Programmable Gate
Array (FPGA)
2. DLL
blocks in FPGAs |
2 hrs |
à Training
Board Description
and Flasher on FPGA Training
Kit
à UP & DOWN
Counter and
7-Segment Display Panel
Interface on FPGA Training Kit
|
|
2 |
2 hrs |
1.
Introduction to configuration, Xilinx
PROM, OTP & In System
Programmable, Configuration Modes,
Master Serial Mode, Slave Serial
Mode, SelectMap Mode, JTAG or
Boundary Scan Mode
2.
Configuration Modes, Master
Serial Mode, Slave Serial Mode,
SelectMap Mode, JTAG or Boundary
Scan
Mode
|
2 hrs |
à LCD
Interface with FPGA
Training Kit
à Traffic
Controller on
FPGA Training Kit
|
|
3 |
2 hrs |
1. UART-transmitter
on FPGA
Development Board |
2 hrs |
à UART-Receiver
on FPGA
Development Board |
6th Week:
|
DAY |
TIME |
TOPIC |
TIME |
LAB WORK |
|
1 |
2 hrs |
1. Real
time debugging for Xilinx FPGA
by
using Xilinx ChipScope Pro
|
2 hrs |
à Monitor
internal signals of
UART core by using ChipScope
|
|
2 |
2 hrs |
1.
System-on-Chip Concept
2. New
Trends in VLSI Industry |
2 hrs |
à Monitor
internal signals of UART
Core by using ChipScope
|
|
3 |
2 hrs |
Case
Study |
2 hrs |
à Case
Study |
Note:
The Lecture/LAB contents may be changed slightly during the course.
Optional:*
The group of Two/Three participants will be presented their assigned
projects with complete RTL, test bench and synthesis results.
Projects, which should be state machine based, will be discussed
individually with participants.
|
Starting From |
Timing |
Last Date of Registration |
Fee |
|
11-10-12 |
1700-2100
(Thu-Fri-Sat) |
08-10-12 |
15,000 |
*
10 % discount for groups only.
Duration = 72 Hours
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